The present invention relates to a method of piping defect detection in semiconductor fabrication, and more particularly, to a method of piping defect detection in inter-layer dielectric layers.
In semiconductor fabrication, after electrical elements, such as metal oxide semiconductor (MOS) transistors, are formed in a substrate, a dielectric layer, referred to as an inter-layer dielectric layer, is typically formed thereon for isolation and protection of electrical elements beneath. Normally, a plurality of contact holes is formed in the inter-layer dielectric layer to fill a conductive layer, used to form a contact plug in each contact hole. Thus, the electrical elements connect with other external electrical elements, such as a conductive wire, through the contact plugs. Data signals are thus transferred to the electrical elements, such as a source or a drain of a transistor, through the conductive wire and the contact plugs to control the operation of each electrical element.
FIGS. 1A to 1B show conventional fabrication of a contact plug in a DRAM. As shown in FIG. 1A, a wafer 10 comprises a substrate 12, preferably silicon, on which an isolation structure 13 is formed to define an active area by, for example, local oxidation of silicon (LOCOS) or shallow trench isolation (STI). Transistors 14, 16, 18, and 20 are disposed on the surface of the substrate 12. The transistor 14 uses the polysilicon layer as the gate with the transistor 18 and the doped region as the source with the transistor 16. In the same manner, the transistor 20 shares a polysilicon layer with the transistor 16 and a source with transistor 18.
As shown in FIG. 1B, a dielectric layer 22, such as a borophospho-tetra-ehtyl-ortho silicate (BPTEOS) layer, is deposited on the wafer 10 by film deposition such as low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or plasma enhanced chemical vapor deposition (PECVD). Photo-etching forms a plurality of contact holes in the dielectric layer 22, and a conductive layer (not shown), such as a polysilicon layer, is deposited on the dielectric layer 22 to fill the contact holes to form contact plugs 26, 28, 30, 32, 34, and 36.
With reduced process size and increased integration, a plurality of voids 24 with piping shapes easily form among gates due to the low filling capability of the dielectric layer 22, connecting contact holes. Although rapid heat treatment is often used to reflow to reduce voids 24 in the dielectric layer 22, such voids cannot be avoided completely. Some contact plugs thus connect or short with each other, such as contact plugs 34 and 36 shown in FIG. 1B, causing the transistors 14, 16, 18 and 20 do malfunction, referred to as piping defects.
Normally electrical elements exhibiting these defects may not be identified for several months since the processes are at the front end of semiconductor fabrication, such that failed electrical elements can only be detected after production. In addition, conventional methods for piping defect detection are incomplete detection with online monitoring due to long treatment time and detection time. Manufacturers normally sample products online, but this does not completely solve the problems and creates higher costs.
Consequently, a simple, effective, online method of piping defect detection is needed.
A method of piping defect detection is disclosed in U.S. Pat. No. 6,825,119, in which a polysilicon layer formed on the dielectric layer electrically connects to electrical elements through contact holes in the dielectric layer. Chemical mechanical polishing removes the polysilicon layer and parts of the dielectric layer. Wet etching removes parts of the dielectric layer. The sample is inspected under UV to detect piping defects according to brightness contrast between the polysilicon layer and the silicon oxide layer. Real-time automatic defect classification (ADC) can be applied to detect the online samples, such that yield and reliability are improved.